The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a high-speed failure capture apparatus and method for use in a semiconductor device tester.
Semiconductor memory manufacturers continuously seek to minimize the costs of producing memory devices in order to remain competitive. One of the more important fabrication processes involves testing each device to ensure reliability and operability under various conditions. The equipment utilized to carry out the testing is often referred to as automatic test equipment, or xe2x80x9ctestersxe2x80x9d.
Conventional testers generally include circuitry that couples to one or more memories-under-test (MUT) and writes signals to selected locations in the MUT. The written signals are subsequently read back and captured by the tester for comparison with expected signals. The failure results of the comparison generally dictate whether the MUT passed the test or requires repair.
Many memory devices employ redundant rows and columns for use in repairing the device should fails be detected during testing. This feature substantially improves the yields in the numbers of commercially acceptable devices. Conventional memory testers typically include one or more redundancy repair stations to physically replace one or more rows or columns with available redundant rows/columns. Before the redundancy analysis can take place, however, the reliable initial capture of the failure data by the tester must occur.
Traditionally, testers have initially stored failure data in RAM memories having overall capacities similar in size to the MUT. Commonly referred to as catchrams or error catch memories, the circuits typically store fail information at addresses that physically correspond to the address locations within predetermined regions of the MUT. This approach conveniently provides a bit-image representation of the MUT region (which may be the entire capacity of the MUT), allowing a user to quickly identify clusters of fails that might relate to a particular fabrication problem. This is particularly important in an engineering development environment to diagnose processing problems in fabricating MUTs early on. Quick identification of processing problems in a production line is also important to minimize any downtime on the line and maximize product throughput and corresponding lot yields.
One construction of a catchram utilizes a 1-bit wide SRAM having an overall storage capacity substantially equivalent to that of a MUT. Known for it""s relatively high speed of operation in random mode, the SRAM provides a desirable memory type from the standpoint of operation. Unfortunately, SRAM production has dropped in recent years, with future availability doubtful. Consequently, the cost of an SRAM device is fairly high.
In an effort to create an SRAM-less catchram, those skilled in the art have utilized various DRAM implementations. DRAMs are relatively inexpensive and generally provide large capacity memories suitable for bit-image catchram applications in some circumstances. The devices include selectable modes of operation according to either a random mode (interleave) or burst mode (sequential). Unfortunately, in the random mode, DRAMs operate at substantially slower speeds than SRAM devices, requiring special techniques in order to operate successfully in catchram applications.
One proposal for using DRAMS in a failure capture memory, disclosed in U.S. Pat. No. 5,790,559 to Sato, employs a large number of banks of interleaved DRAMs to achieve acceptable speeds of operation during the DRAM random (interleaving) mode. The banks each have an overall storage capacity equivalent to that of the MUT and produce outputs that are interleaved to generate a faster serial bitstream. As an alternative to the random mode of operation, the patent also discloses a technique that uses the DRAM burst mode in combination with an address converter to simultaneously store multiple bits of fail data sequentially in the DRAM memory banks.
While the Sato proposals appear beneficial for their intended applications, they employ many banks of DRAM devices for each MUT, with the appearance of no real guarantee of a non-random mode operation. For example, if a read of the MUT involves switching rows or columns a number of times, the operation approaches a slower random-type mode. This defeats the use of the DRAM burst feature. To address this problem, it is believed that the Sato implementations require an undesirably high number of DRAM banks, or in the alternative require specialized test patterns. Implementing special test patterns is not only costly from a development standpoint, but problematic because of the limited number of devices that could be tested.
Conventional semiconductor testers also typically provide a testhead construction that positions arrays of pin electronics boards into close proximity to the DUT""s to minimize propagation delays and related effects. The pin electronics boards generally include the capture and compare circuitry necessary to extract and detect the failures for the catchram memory. The typical testhead/mainframe construction generally results in a fairly large cable bundle that interconnects the testhead with the tester mainframe (where the catchram memories usually reside). The cable bundle is not only difficult to manipulate, but costly in terms of the actual cable expense and the overall tester xe2x80x9cfootprintxe2x80x9d within the manufacturing clean room. With proposed semiconductor devices requiring 1024 channels or more, the number of cables necessary to support conventional testhead constructions becomes problematic.
Another problem with conventional ATE failure processing systems involves the transfer time of the failure data from the testhead to the mainframe (over the cable bundle), and from the output of the failure memory to the repair analysis circuitry, commonly referred to as redundancy analyzers (RAs). Typically, the system pattern generator drives the transfer of data from the memory to the RA during a brief xe2x80x9choldingxe2x80x9d period (where no capture of data occurs). This is believed to undesirably extend the time required to test a DUT, consequently reducing throughput.
A related problem to the transfer of data between the memory and the RA for conventional testers involves the routing of the memory output to a particular RA. Generally, regions or xe2x80x9cslicesxe2x80x9d of conventional catchram memory configurations have respective outputs hard-wired to predetermined. RA""s. This construction has been determined to unnecessarily limit the transfer bandwidth and cause other undesirable transfer restrictions.
What is needed and heretofore unavailable is a catchram memory construction that provides the capability of reconstructing a bit image map of the failure data from one or more MUTs with minimal hardware cost. Moreover, the need exists for such a circuit construction that also provides maximum data transfer rates with minimal cost. The failure capture circuit and method of the present invention satisfies these needs.
The failure capture circuit of the present invention reduces costs involved in capturing and analyzing failure data from a memory-under-test (MUT). This is accomplished by implementing a minimal number of DRAM banks that are configured to allow the transfer of output failure data via an interleave mode of operation. Moreover, the transfer of failure data to and from the memory banks is carried out at high speed to minimize test time.
To realize the foregoing advantages, the invention in one form comprises a failure capture circuit for use in a failure processing circuit to identify failure location information from a memory-under-test (MUT). The failure capture circuit includes failure detection circuitry comprising a plurality of channels and adapted for coupling to the MUT. The failure detection circuitry is operative to apply test signals to the MUT and process output signals therefrom into failure information. Memory is provided in the failure capture circuit having a capacity corresponding to a predetermined portion of the MUT. A high-speed link couples the memory to the failure detection circuitry.
In another form, the invention comprises a failure capture circuit for use in a failure processing circuit to identify failure location information from a memory-under-test (MUT). The failure capture circuit includes failure detection circuitry comprising a plurality of channels and adapted for coupling to the MUT. The failure detection circuitry is operative to apply test signals to the MUT and process output signals from the MUT into failure information. The failure capture circuit further includes a failure memory circuit having memory comprising a plurality of memory banks. The banks have substantially similar address rows and columns and are configured to receive the failure signals in a random mode. The failure memory circuit also includes reconcile circuitry coupled to respective burst mode outputs in the banks and having a reconcile path to the bank inputs. The reconcile circuitry is operative to, after the banks have captured a predetermined amount of data, ensure that each of the substantially similar addresses of the banks contains the same data.
In yet another form, the invention comprises a failure processing circuit for determining failure data from a MUT and analyzing the failure data to repair the MUT. The failure processing circuit includes a failure capture circuit having failure detection circuitry responsive to a first pattern generator and adapted for coupling to the MUT. The failure detection circuitry is operative to apply test signals to the MUT and process output signals from the MUT into failure information. The failure capture circuit further includes a failure memory circuit having a storage capacity corresponding to predetermined portions of the MUT and output transfer circuitry. Redundancy analysis circuitry is included to establish a procedure for repairing the MUT along with a second pattern generation circuit. The second pattern generation circuit is operative to support the transfer of failure data along the output transfer circuitry independent from the first pattern generator.
A further form of the invention comprises a failure capture circuit for use in a failure processing circuit to identify failure location information from a memory-under-test (MUT). The failure capture circuit includes failure detection circuitry comprising a plurality of channels. The failure capture circuit is adapted for coupling to the MUT and operative to apply test signals to the MUT and process output signals from the MUT into failure information. A failure memory circuit is included that has a capacity corresponding to a predetermined portion of the MUT and further includes slice circuitry corresponding to predetermined MUT storage regions. The failure memory circuit also includes transfer circuitry comprising an output selector for routing the slice output to the redundancy analysis circuitry.
In another form, the invention comprises a method of acquiring multiple channels of failure information from a MUT for subsequent redundancy analysis. The method includes the steps of capturing the failure information in a testhead failure capture circuit; and serially transmitting the captured failure information along a high speed link to a failure memory circuit having a memory capacity corresponding to a predetermined portion of the MUT.
In yet another form, the invention comprises a method of acquiring multiple channels of failure information from a MUT for subsequent redundancy analysis. The method includes the steps of capturing the failure information in a testhead failure capture circuit; randomly storing the failure information in a failure memory circuit that includes a plurality of memory banks having respective burst mode outputs; and reconciling the failure data within the plurality of memory banks. The reconciling step includes the steps of bursting the failure information out of the plurality of memory banks to a cache memory, and bursting back the burst data from the cache memory to the plurality of memory banks such that each of the banks reflects the same failure information in like addresses.
In another form, the invention comprises a method of acquiring and processing multiple channels of failure information from a MUT. The method includes the steps of capturing the failure information with failure detection circuitry in conjunction with a first pattern generation circuit; storing the failure information in a memory having a capacity corresponding to a predetermined portion of the MUT; and transferring the failure information from the memory in conjunction with a second pattern generation circuit independent of the first pattern generation circuit.
In yet another form, the invention comprises a method of acquiring and processing multiple channels of failure information from a MUT. The method includes the steps of capturing the failure information with failure detection circuitry; storing the failure information in a memory having a capacity corresponding to a predetermined portion of the MUT; and selectively routing the failure information from the memory to a redundancy analysis circuit.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.